Address decoding is carried out by the PAL (IC36) and this then selects either the operating system (if the address is in the range &C000-&FFFF) or the current sideways ROM (if the address is in the range &8000-&BFFF). Part of IC40 disables the ROM output drivers when an I/O address occurs (&FC00-&FEFF). The currently selected ROM number (0-15) is held in the ROM select latch IC45. The ROM select latch is mapped into the memory at address &FE30 via the PAL IC36. When writing to this address, the four data lines D0-D3 provide the ROM number which is latched into IC45, see also 5.4.2. When the PAL decodes an address from &8000-&BFFF, IC36 pin 18 goes low and enables IC46.
IC46 is a three line to eight line decoder which selects the particular IC socket allocated to the ROM number, in IC45. The least significant bit held in IC45 is fed to the relevant ROM socket only if the link for that socket is made E for a 32K device. The correct half of the 32K device is then selected to be placed in the memory map. 5.4.2 Paged RAM operation The 12K paged RAM is selected with a ROM number between 128 and 255 ( D7 set). The top bit of the data bus D7 is available to the PAL IC36. Writing to the ROM select latch at address &FE30 as described in 5.4. 1, will save D7 in the PAL. D0-D3 are stored as normal in IC45.
If D7 is set (logic 1) then the PAL selects the 12K paged RAM when the CPU address is in the range &8000 to &AFFF. If the ROM selected by D0-D3 is present then the top 4K of that ROM will also appear in the memory map, above the 12K paged RAM, from &B000-&BFFF. As ROM 0 is not allocated as standard (it is BASIC if S13 is changed), writing 128 to the ROM select latch will merely place the 12K paged RAM into the memory map and &B000-&BFFF will be vacant. 5.4.3 RAM access There is 64K of installed RAM. RAM access is dependent on whether the computer is in normal mode or shadow mode, and the differences are shown in Figure 5. 16