Digital I/O High-Speed Interrupts Normally, the digital I/O system is checked once every eV+ major cycle (every 16 ms). In some cases, the delay or uncertainty resulting may be unacceptable. Digital signals 1001 - 1004 can be configured as high-speed interrupts. When a signal configured as a high-speed interrupt transitions, its state is read at system interrupt level, resulting in a maximum delay of 1 ms. The ACE software Controller Configuration Tools are used to configure high-speed interrupts. Soft Signals Soft signals are used primarily as global flags. The soft signals are in the range 2001 - 2512 and can be used with SIG and SIGNAL.
A typical use of soft signals is for intertask communication. See "REACT and REACTI" and the REACT_ instructions in the eV+ Language Reference Guide . Digital I/O and Third Party Boards When eV+ starts, default blocks of system memory are assigned to the digital I/O system. eV+ expects to find the digital I/O image at these locations. If you are using a third party digital I/O board, you must remap these memory locations to correspond to the actual memory location of the digital I/O image on your board. See the description of DEF.DIO in the eV+ Language Reference Guide for details.
Digital I/O and DeviceNet When eV+ starts, default blocks of system memory are assigned to the DeviceNet system. eV+ expects to find the DeviceNet image at these locations. For additional information, see DeviceNet on page 156. eV+Language User's Guide, v2.x, 18318-000 Rev A Page 138