16 CP1E E/NS-type Item CP2E E/S-type CPU Units CP1E N-type CPU Units CP2E N-type CPU Units CPU Units Option Boards that can be mounted Cannot be mounted.
• RS232C Option Board CP1W-CIF01 • RS422A/485 Option Board CP1W-CIF11/CIF12-V1 • Ethernet Option Board CP1W-CIF41 • Analog Option Board CP1W-MAB221/ADB21/ DAB21V Serial Communication Option Board with one port • RS232C Option Board CP1W-CIF01 • RS-422A/485 Option Board CP1W-CIF11/CIF12-V1 Serial Communication Option Board with two ports*1 • RS232C Option Board CP2W-CIFD1 • RS232C & RS-485 Option Board CP2W-CIFD2 • RS-485 Option Board CP2W-CIFD3 Analog Option Board*2 CP1W-MAB221/ ADB21/ DAB21V *1 CP2W-CIFD can only be mounted on option slot 1. *2 Maximum one Analog Option Board can be mounted on an N-type CPU Unit. Memory backup Built-in EEPROM:
Contains the user programs, parameters, DM Area initial values and comment files Built-in SRAM (Battery backup): DM/HR/CNT/AR Data memory area Built-in Flash Memory: Contains the user programs, parameters, DM Area initial values and comment files Built-in non-volatile memory (Batteryless backup): DM/HR/CNT/AR Data memory area Built-in EEPROM: Contains the user programs, parameters, DM Area initial values and comment files Built-in SRAM (Battery backup): DM/HR/CNT/AR Data memory area Built-in Flash Memory: Contains the user programs, parameters, DM Area initial values and comment files Built-in non-volatile memory (Batteryless backup): DM/HR/CNT/AR Data memory area Clock ES-type:
Not supported NS-type: Supported E-type: Not supported S-type: Supported Supported Supported Item CP1E CPU Units CP2E CPU Units Program capacity E-type: 2K steps N-type: 8K steps E-type: 4K steps S-type: 8K steps N-type: 10K steps FB capacity Not provided E-type: 4K steps S-type: 8K steps N-type: 10K steps Program language Ladder diagram Ladder diagram Function blocks Not provided Maximum number of function block definitions: 64 Maximum number of instances: 128 Languages usable in function block definitions: Ladder diagrams, structured text (ST) Instructions Approximately 200 Approximately 220 Instruction execution times LD: 1.19 μs MOV: 7.9 μs LD: 0.23 μs MOV:
1.76 μs Number of tasks 17 • 1 cyclic task • 16 interrupt tasks 17 • 1 cyclic task • 16 interrupt tasks Maximum subroutine number 128 128 Maximum jump number 128 128 Scheduled interrupt tasks 1 1 CIO Area 4,640 bits (290 words) CIO 0.00 to CIO 289.15 (CIO 0 to CIO 289) 4,640 bits (290 words) CIO 0.00 to CIO 289.15 (CIO 0 to CIO 289) Work Area (W) 1,600 bits (100 words) W0.00 to W99.15 (W0 to W99) 2,048 bits (128 words) W0.00 to W127.15 (W0 to W127) Holding Area (H) 800 bits (50 words) H0.00 to H49.15 (H0 to H49) 2048 bits (128 words) H0.00 to H127.15 (H0 to H127) Auxiliary Area (A) Read-only: 7,168 bits (448 words) A0.00 to A447.15 (A0 to A447) Read/write:
4,896 bits (306 words) A448.00 to A753.15 (A448 to A753) Read-only: 7,168 bits (448 words) A0.00 to A447.15 (A0 to A447) Read/write: 8,192 bits (512 words) A448.00 to A959.15 (A448 to A959) Temporary Area (TR) 16 bits: TR0 to TR15 16 bits: TR0 to TR15 Counter Area (C) 256 timer numbers: T0 to T255 256 timer numbers: T0 to T255 Timer Area (T) 256 counter numbers: C0 to C255 256 counter numbers: C0 to C255 Data Memory Area (D) E-type: 2K words D0 to D2047 N-type: 8K words D0 to D8191 E-type: 4K words D0 to D4095 S-type: 8K words D0 to D8191 N-type: 16K words D0 to D16383 Data Registers (DR) Not provided 16 registers: DR0 to DR15 Index Registers (IR) Not provided 16 registers:
IR0 to IR15