1-10 IC12, 16 ALVCH16245 (16 bit Bus bidirectional transceivers) 1-11 IC13-15 ALVCH16244 (16 bit Bus Buffers) 1-12 IC17, 18 LVC244 (8 bit Bus Buffers) 1-13 IC19 LVC245 (8 bit Bus bidirectional transceivers) In particular, this is used for changing 5V into 3.3V. 1-14 IC20 M51957B (System Reset IC. Delay time is about 0.34 sec) 1-15 IC21, 22 NJM317 (Regulator IC) IC21: regulate +2.5V for FPGA. IC22: regulate +1.75V for CPU. 1-16. IC23 NET2890 (USB function controllers) 1-16-2. Pin Descriptions (PU:pull-up, PD:pull-down) SERVICE MANUAL 26 Pin No. Signal name Dir Explanation 2 /SOF out Start of Frame. Active low. 3,4 DP,DM i/o USB data port. differential data.
5-11 D[7:0] i/o bi-directional 8-bit data bus. Connected with CPU for communication. 14 15 /CS in Chip select. Active low. (PU) 16 LCLK out buffered clock output. 17 /IOR in I/O read strobe. Active low. (PU) 18 /IOW in I/O write strobe. Active low. (PU) 19 DRQ out DMA request. 20 /DACK in DMA acknowledge. Active low. (PU) 21 /EOT in End of transfer. Active low. (PU) 22 /BUSPWR in Indicates that external logic is powered by USB bus. Alternatively general input. 23 /PWRGOOD in Indicates that external power supply used for self-powered mode is operational. Alternatively general input. 26 /IRQ out Interrupt Request. Active low. 27 /USBOE i/o USB port output enable. Active low.
(PU) 28 /DEVCFG out Device config. Alternatively general output. (PD) 30 TEST in Test. Connect this pin to ground. (PD) 32 /LRESET out Local reset. Active low. (PU) 33 /SUSP out Device suspended. Active low. (PU) 34 /WAKEUP in USB remote wakeup. Active low. (PU) 35 /RESET in External reset. (PU) 38-42 A[4:0] in Address bus. 44 CLKIN in 48 MHz Oscillator input. 45 CLKOUT out 48 MHz Oscillator output. 47 TESTOUT out Test output. Used for manufacturing test. 31 VDD LOCAL _ - +3.3V or +5V DC power input for CPU I/F. 1,13,25 37,43 VDD - +3.3V DC power input for the core and USB I/F. 12,24,36 46,48 Vss - GROUND. 0V DC power return.