INSTRUCTION EXPLANATION [ ... other instructions ... ] WAIT for position (0,255) At this point, the vertical counter appears to wrap to 0 because the comparison works on the least significant bits of the vertical count. WAIT for any horizontal position with Thus the total of 256+6 = 262 vertical position 0 through 256, covering lines of video beam travel the last 6 lines of the scan before vertical during which Copper blanking occurs. instructions can be executed. NOTE The vertical is like the horizontal - as there are alternating long and short lines, there are also long and short fields (interlace only). In NTSC, the fields are 262, then 263 lines and in PAL, 312,313.
This alteration of lines & fields produces the standard NTSC 4 field repeating pattern: short field ending on short line long field ending on long line short field ending on long line long field ending on short line & back to the beginning... 1 horizontal count takes 1 cycle of the system clock. (Processor is twice this) NTSC- 3,579,545 Hz PAL- 3,546,895 Hz genlocked- basic clock frequency plus or minus about 2%. THE COMPARISON ENABLE BITS Bits 14-1 are normally set to all 1s. The use of the comparison enable bits is described later in the "Advanced Topics " section. - Coprocessor Hardware 19 -