The CPU is normally clocked at 2MHz. The 6512 (IC42) requires a two phase non-overlapping clock on inputs phil (pin 3) and phi2 (pin 37), see figure 1. Figure 1 Non-overlapping clock inputs phil and phi2 Phil and phi2 are generated by IC33, two gates of which are used to build an R-S latch. Not2M from IC26 is used to set and reset the R-S latch which toggles at 2MHz unless a third gate from IC33 blocks the not2M signal. During 2MHz operation the phi2 clock corresponds to not2M, the inverse of 2M from the video processor. When accessing slow devices (1MHz extension bus, ADC, VIAs, 6845, ACIA, and serial processor) the clock is stretched to give a pseudo 1MHz cycle.
The system 1MHz clock, E, is generated in half of IC25 from the 1MHz and 2MHz outputs of the video processor. The other half of IC 25 is used to synchronise the transition from 2MHz to 1MHz clocking. Each 1 MHz peripheral select line is connected to an input of NAND gate IC41. If any input of this NAND gate is taken to logic 0 then a 1MHz CPU cycle will occur. For 1MHz cycles phi2 is held at logic 1 until the 1E signal is synchronised. The cycle ends with both phi2 and 1E falling together. 12