The bit interval timer is designed to detect an interval of approx 6. 5us. Disc speed is measured by timing the interval between index pulses, which are nominally 200ms apart. One interval timer IC4 is used for both RDY0 and RDY1. 16/13 MHz (1.2307MHz) is used to clock a binary counter (IC4). When all drives are off, the MOTOR signal will be high (off). Motor off forces both stages of IC3 to predefined states, IC3 pin 13 is high and IC3 pin 2 (notRDY) is high. A drive is turned on when MOTOR goes law. IC3 can now be clocked by index pulses and so detect the state of the digital timer IC4.
If IC4 pin 11 goes high then the interval between index pulses is greater than 213ms (2^18*812.5ns),and the disc speed is too slow. If IC4 pin 11 is still at logic 0 when an index pulse occurs then the disc speed is taken to be almost right, so that after one additional disc revolution the speed can be assumed within working limits. IC3 pin 13 is clocked low if IC4 pin 11 is low when an index pulse occurs. If IC3 pin 3 is still low at the next index pulse then IC3 pin 2 will go law, indicating that the drive is ready. Diode Dl and resistor R2 OR the MOTOR signal and the state of IC4 pin 11.
The OR function means that whenever IC4 pin 11 goes high it will set IC3 pin 13, and the RDY generation sequence is returned to the beginning. Resetting IC3 by IC4 pin 11 avoids a false RDY if the drive is very slow, when IC4 pin 11 might go high then low between two index pulses. Communication between the 8271 disc controller and the microprocessor occurs at two levels: Commands to the disc controller are made by normal program controlled accesses to the I/O space between addresses &FE80 and &FE83. Bytes of data transferred between the disc and the controller are processed using an NMI interrupt routine which demands immediate action from the CPU.
The interrupt program code accesses the 8271 at address &FE84; this address is for DACK controlled transfers. When a DACK controlled transfer is required the 8271 generates an interrupt by setting pin 11 high (of IC15). The interrupt request is inverted by IC7, an open collector NAND gate, to become notNMI. NotNMI is a wire NUR signal which passes directly to the CPU notNMI input (IC42 pin 6) via an AND gate (IC34). Address decoding for the disc controller is done by three ICs. IC22 pin 8 goes low when the CPU address is greater than &FC00, and so enables the I/O decoding logic. IC21 generates the notFDC signal which is low for address values &FE80 to &FE9F.
The final decode is by IC28 which splits the notFDC space into blocks of four using the A2 address. IC28 pin 12 is low for &FE80 to &FE83 which is the notCE address for the 8271 disc controller. NotDACK is low for &FE84 to &FE87. Pin 15 of IC28 is held permanently low (link S7 West) as 8271 interface timing is controlled by not2M through the notR and notW signals (from IC27). 20