6 Application Instructions API 00-49 API 34 Operands: S : Start No. of the shifted device D : Start No. of the device to be shifted n 1 : Length of data to be shifted n 2 : Number of bits to be shifted in 1 shift Explanations: 1. Range of n 1 : 1~ 1,024 2. Range of n 2 : 1 ~ n 1 3. In ES/EX/SS, 1 ≤ n 2 ≤ n 1 ≤ 512 4. ES/EX/SS series MPU does not support E, F index register modification. 5. See the specifications of each model for their range of use. 6. This instruction shifts the bit device of n 1 bits (desired length for shifted register) starting from D to the right for n 2 7. This instruction adopts pulse execution instructions (SFTRP). bits.
S is shifted into D for n 2 bits to supplement empty bits. Program Example: 1. When X0 = Off→On, M0 ~M15 will form 16 bits and shifts to the right (4 bits as a group). 2. The figure below illustrates the right shift of the bits in one scan. M3 ~ M0 → carry M7 ~ M4 → M3 ~ M0 M11 ~ M8 → M7 ~ M4 M15 ~ M12 → M11 ~ M8 X3 ~ X0 → M15 ~ M12 completed 4 bits as a group shifting to the right 5 carry 1 2 3 4 DVP-PLC Application Manual 6-54 Mnemonic Operands Function SFTR P Bit Shift Right Type OP Bit Devices Word Devices Program Steps X Y M S K H KnX KnY K nM Kn S T C D E F SFTR, SFTRP:
9 steps S * * * * D * * * n 1 * * n 2 * * PULSE 16-bit 32-bit EH3 EH3 ES EX SS SA SX SC EH SV EH3 SV2 ES EX SS SA SX SC EH SV ES EX SS SA SX SC EH SV SV2 SV2 X0 S FTR X0 M0 K16 K4 X3 X2 X1 M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0