10 Application Instructions API 202-313 API 207 Operands: S : Source device of signal input (Only X0 and X1 are available) S 1 : Sample time setting and the input speed information D : Output proportion setting and output speed information Explanations: 1. When S specifies X0, PLC only uses X0 input point and its associated high speed pulse output: Y0, in this case Y1 is normal output point. When S specifies X1, PLC uses X0 (A phase) and X1 (B phase) input points and their associated output: Y0 (Pulse) / Y1 (Dir). 2. The execution of CSFO requires hardware high speed counter function as well as the high speed output function.
Therefore, when program scan proceeds to CSFO instruction with high speed counter input points (X0, X1) enabled by DCNT instruction, or high speed pulse outputs (Y0, Y1) enabled by other high speed output instructions, CSFO instruction will not be activated. 3. If S specifies X1 with 2-phase 2 inputs, the counting mode is fixed as quadruple frequency. 4. During pulse output process of Y0, special registers (D1337, D1336) storing the current number of output pulses will be updated when program scan proceeds to this instruction. 5. S 1 occupies consecutive 4 16-bit registers. S 1 +0 specifies the sampling times, i.e.
when S 1 +0 specifies K1, PLC catches the speed every time when 1 pulse is outputted. Valid range for S 1 +0 in 1-phase 1-input mode: K1~K100, and 2-phase 2-input mode: K2~K100. If the specified value exceeds the valid range, PLC will take the lower/upper bound value as the set value. Sample time can be changed during PLC operation, however the modified value will take effect until program scan proceeds to this instruction. S 1 +1 indicates the latest speed sampled by PLC (Read-only). Unit: 1Hz. Valid range: 10kHz. S 1 +2 and S 1 +3 indicate the accumulated number of pulses in 32-bit data (Read-only). 6.
For single phase input, the max frequency is 10kHz; for 2-phase 2 inputs, the max frequency is 2kHz. 7. D occupies 3 consecutive 16-bit registers. D +0 specifies the output proportion value. Valid range: K1 (1%) ~ K10000 (10000%). If the specified value exceeds the valid range, PLC will take the lower/upper bound value as the set value. Output proportion can be changed during PLC operation, however the modified value will take effect until program scan proceeds to this instruction. D +2 and D +1 indicates the output speed in 32-bit data. Unit: 1Hz. Valid range: 100kHz. 8.
The speed sampled by the PLC will be multiplied with the output proportion D +0, then the PLC will generate the actual output speed. The PLC will take the integer of the calculated value, i.e. if the calculated result is smaller than 1Hz, the PLC will output with 0Hz. For example, input speed: 10Hz, output proportion: K5 (5%), then the DVP-PLC Application Manual 10-13 Mnemonic Operands Function CSFO Catch speed and proportional output Type OP Bit Devices Word devices Program Steps X Y M S K H KnX KnY KnM KnS T C D E F CSFO: 7 steps S * S 1 * D * PULSE 16-bit 32-bit ES EX SS SA SX SC EH SV EH3 SV2 ES EX SS SA SX SC EH SV EH3 ES EX SS SA SX SC EH SV EH3 SV2 SV2