Chapter 1: Introduction 1-4 Chipset Overview The H8DCE serverboard is based on the nVidia nForce Pro 2200/2050 chipset. The two main components of this chipset (the 2200 and the 2050) both function as Media and Communications Processors (MCPs). Controllers for the system memory are integrated directly into the AMD Opteron processors. 2200 Media and Communications Processor This MCP is a single-chip, high-performance HyperTransport peripheral control- ler. The 2200 includes a 20-lane PCI Express interface, an AMD Opteron 16-bit Hyper Transport interface link, a four-port Serial ATA interface, a dual ATA133 bus master interface, a USB 2.0 interface and support for 32-bit PCI slots.
This hub connects directly to CPU#1 and the 2050 MCP. The GLAN#1 connects directly to the 2200 MCP. 2050 Media and Communications Processor The 2050 is pin-to-pin compatible with the 2200. It includes a PCI Express interface with 20 lanes, an AMD Opteron 16-bit Hyper Transport interface link, and a four-port Serial ATA interface. The GLAN#2 connects directly to the 2050 MCP. HyperTransport Technology HyperTransport technology is a high-speed, low latency point to point link that was designed to increase the communication speed by a factor of up to 48x between integrated circuits.
This is done partly by reducing the number of buses in the chipset to reduce bottlenecks and by enabling a more effi cient use of memory in multi-processor systems. The end result is a signifi cant increase in bandwidth within the chipset. 1-9