intel MCS BASIC-52 — Intel MCS BASIC-52 Versions 1 & 1.1 Operating and Reference Manual PDF (EN)

int e l 1.11 8052AH SPECIAL FUNCTION REGISTERS (MSB) (LSB) (MSB) (LSB) Symbol Position Function -- IP.7 reserved -- IP.6 reserved PT2 IP.5 defines the Timer 2 interrupt priority level. PT2 = 1 programs it to the higher priority level. PS IP.4 defines the Serial Port interrupt priority level. PS = 1 programs it to the higher priority level. PT1 IP.3 defines the Timer 1 interrupt priority level. PT1 = 1 programs it to the higher priority level. PX1 IP.2 defines the External Interrupt 1 priority level. PX1 = 1 programs it to the higher priority level. PT0 IP.1 defines the Timer 0 interrupt priority level. PT0 = 1 programs it to the higher priority level.

PX0 IP.0 defines the External Interrupt 0 priority level. PX0 = 1 programs it to the higher priority level. Symbol Position Function EA IE.7 disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. -- IE.6 reserved ET2 IE.5 enables or disables the Timer 2 overflow or capture interrupt. If ET2 = 0, the Timer 2 interrupt is disabled. ES IE.4 enables or disables the Serial Port interrupt. If ES = 0, the Serial Port interrupt is disabled. ET1 IE.3 enables or disables the Timer 1 Overflow interrupt. If ET1 = 0, the Timer 1 interrupt is disabled.

EX1 IE.2 enables or disables External Interrupt 1. If EX1 = 0, External Interrupt 1 is disabled. ET0 IE.1 enables or disables the Timer 0 Overflow interrupt. If ET0 = 0, the Timer 0 Interrupt is disabled. EX0 IE.0 enables or disables External Interrupt 0. If EX0 = 0, External Interrupt 0 is disabled. IP: Interrupt Priority Register IP: Interrupt Enable Register - 198 - X X PT 2 PS PT 1 PX 1 PT 0 PX 0 EA X ET 2 ES ET 1 EX 1 ET 0 EX 0