intel MCS BASIC-52 — Intel MCS BASIC-52 Versions 1 & 1.1 Operating and Reference Manual PDF (EN)

int e l Table B-1. Instruction Set Summary (Cont'd.) The source data address (second data address) is encoded in the first byte following the opcode. The destination data address is encoded in the second byte following the opcode. - 205 - Mnemonic Operation Cycles Binary Code Flags P OV AC C Function MOV Rr,data addr (Rr) 2 1 0 1 0 1 r r r m m m m m m m m Move contents of data address to register. MOV bit addr,C (bit address) 2 1 0 0 1 0 0 1 0 b b b b b b b b Move C to bit. MOV data addr,#data (data address) 2 0 1 1 1 0 1 0 1 m m m m m m m m d d d d d d d d Move immediate data to data address.

MOV data addr,@Rr (data address) 2 1 0 0 0 0 1 1 r m m m m m m m m Move contents of indirect address to data address. MOV data addr,A (data address) 1 1 1 1 1 0 1 0 1 m m m m m m m m Move A to data address. MOV data addr,Rr (data address) 2 1 0 0 0 1 r r r m m m m m m m m Move register to data address. MOV data addr1,data addr2 (data address1) 2 1 0 0 0 0 1 0 1 m m m m m m m m• m m m m m m m m• Move contents of second data address to first data address. MOVC A,@A + DPTR (PC) 2 1 0 0 1 0 0 1 1 P Add A to DPTR and move contents of that code address with A. MOVC A,@A + PC (A) 2 1 0 0 0 0 0 1 1 P Add A to PC and move contents of that code address with A.

MOVX @DPTR,A DPTR)) 2 1 1 1 1 0 0 0 0 Move A to external data location addressed by DPTR. MOVX @Rr,A ((Rr)) 2 1 1 1 1 0 0 1 r Move A to external data location addressed by register. MOVX A,@DPTR (A) 2 1 1 1 0 0 0 0 0 P Move contents of external data location addressed by DPTR to A MOVX A,@Rr (A) 2 1 1 1 0 0 0 1 r P Move contents of external data location addressed by register to A. MUL AB (AB) 4 1 0 1 0 0 1 0 0 P OV C Multiply A by B (multiplication register). NOP 1 0 0 0 0 0 0 0 0 Do nothing. ORL A,#data (A) 1 0 1 0 0 0 1 0 0 d d d d d d d d P Logical OR immediate data to A. ORL A,@Rr (A) 1 0 1 0 0 0 1 1 r P Logical OR contents of indirect address to A.

ORL A,Rr (A) 1 0 1 0 0 1 r r r P Logical OR register to A. ORL A,data addr (A) 1 0 1 0 0 0 1 0 1 m m m m m m m m P Logical OR contents of data address to A. ORL C,bit addr (C) 2 0 1 1 1 0 0 1 0 b b b b b b b b C Logical OR bit to C.