int e l Table B-1. Instruction Set Summary (Cont'd.) - 207 - Mnemonic Operation Cycles Binary Code Flags P OV AC C Function XCH A,@Rr temp 1 1 1 0 0 0 1 1 r P Move A to indirect address and vice versa. XCH A,Rr temp 1 1 1 0 0 1 r r r P Move A to register and vice versa. XCH A,data addr temp 1 1 1 0 0 0 1 0 1 m m m m m m m m P Move A to data address and vice versa. XCHD A,@Rr temp 1 0 1 1 0 0 1 1 r P Move low order of A to low order nibble of indirect address and vice versa. XRL A,#data (A) 1 0 1 1 0 0 1 0 0 d d d d d d d d P Logical exclusive OR immediate data to A. XRL A,@Rr (A) 1 0 1 1 0 0 1 1 r P Logical exclusive OR contents of indirect address to A.
XRL A,Rr (A) 1 0 1 1 0 1 r r r P Logical exclusive OR register to A. XRL A,data addr (A) 1 0 1 1 0 0 1 0 1 m m m m m m m m P Logical exclusive OR contents of data address to A. XRL data addr,#data (data address) 2 0 1 1 0 0 0 1 1 m m m m m m m m d d d d d d d d Logical exclusive OR immediate data to data address. XRL data addr,A (data address) 1 0 1 1 0 0 0 1 0 m m m m m m m m Logical exclusive OR A to data address.