The RAM control circuit is designed to work with either 128 or 256 refresh cycle DRAMs, refresh being provided by the 6845 CRTC (IC78) in conjunction with two ex-OR gates of IC63 and an AND gate of IC34. The RAM is accessed at 4MHz, the CPU and VDU each having 2MHz access. The address multiplexers for the VDU cycle are ICs 72, 73, 74, and 75. Various combinations of the inputs of these ICs are used depending on the screen mode in use. In particular, TELETEXT mode 7, with its own character generator (IC59) is markedly different from the other seven bit-mapped modes 0-6. The address multiplexers for the CPU cycle are ICs 50 and 51.
RAM is working (being addressed and strobed) the whole time, both during CPU and VDU phases, even when not required (except for the purpose of refresh). But data to or from the RAM is only available to the CPU, when the data buffer IC49 is enabled. This occurs when any input to the NAND gate in half of IC40 goes low, that is when Al5 is low (address between &0000-&7FFF) or if the paged RAM signal fran IC36 is low (address between &8000-&AFFF and paged RAM selected), or if the video processor (VIDPROC) is enabled (address &FE20). RAM is disabled when the VIDPROC is written to, by holding notCAS at logic 1 (see IC23).
5.5 Disc interface There are two floppy disc interfaces which can be fitted to the PCB, based on either the 8271 floppy disc controller for FM only, or the 1770 floppy disc controller for FM and MFM. 5.5.1 8271 FDC Two open collector buffer ICs are used to drive the disc unit. A 7416 (hex inverter, IC8) is used to invert the "true' control signals output by the controller IC15. Two gates from a 7438 (quad NAND gate, IC7) generate the two drive select signals by combining the controller's drive select lines with the load head signal (used as a motor control line). Each data pulse from the drive triggers/retriggers a monostable pulse generator IC1.
The pulse clears an R-S latch formed by two cross- coupled NAND gates (IC9), and clears the bit interval timer formed by two divide by sixteen circuits (IC2) and a NAND gate (IC9). If the bit interval exceeds the time determined by the bit interval timer then the latch will be set (DW=1). The 8271 monitors the latch (the data window) and the read data pulses to decode the serial data stream. If the latch is reset (DW = 0) when a data pulse occurs, the 8271 interprets the bit value as logic 1; conversely if DW = 1 then the data bit is a logic 0. Logic 0 bits are encoded as 8us between RD pulses, logic is as 4us, and each bit interval is 8us. 19