HOW COLLISIONS ARE DETERMINED........................207 HOW TO INTERPRET THE COLLISION DATA .................208 HOW COLLISION DETECTION IS CONTROLLED ...............209 Beam Position Detection.................................210 USING THE BEAM POSITION COUNTER......................210 Interrupts .............................................211 NONMASKABLE INTERRUPT ...............................212 MASKABLE INTERRUPTS..................................212 USER INTERFACE TO THE INTERRUPT SYSTEM ..............212 INTERRUPT CONTROL REGISTERS .........................212 SETTING AND CLEARING BITS............................213 DMA Control ............................................217 Processor Access to Chip Memory.........................217 Reset and Early Startup Operation.......................219 Chapter 8 INTERFACE HARDWARE..............................221 Introduction............................................221 Controller Port Interface...............................222 REGISTERS USED WITH THE CONTROLLER PORT..............223 Floppy Disk Controller .....,.............................235 REGISTERS USED BY THE DISK SUBSYSTEM ................236 DISK INTERRUPTS .....................................244 The Keyboard............................................245 HOW THE KEYBOARD DATA IS RECEIVED....................245 TYPE OF DATA RECEIVED................................245 LIMITATIONS OF THE KEYBOARD .........................247 Parallel Input/Output Interface.........................250 Serial Interface .......................................250 INTRODUCTION TO SERIAL CIRCUITRY ....................250 SETTING THE BAUD RATE................................250 SETTING THE RECEIVE MODE ............................251 CONTENTS OF THE RECEIVE DATA REGISTER................251 HOW OUTPUT DATA IS TRANSMITTED.......................253 SPECIFYING THE REGISTER CONTENTS ....................254 Display Output Connections .............................255 Appendix A Register Summary-Alphabetical Order............257 Appendix B Register Summary-Address Order.................281 Appendix C Custom Chip Pin Allocation List................289 Appendix D System Memory Map..............................293 Appendix E Interfaces ....................................295 Appendix F Complex Interface Adapters.....................317 8520 Complex Interface Adaptor (CIA) Chips..............317 Chip Register Map.......................................319 Register Functional Description.........................320 I/O PORTS (PRA, PRB, DDRA, DDRB).....................320 HANDSHAKING..........................................320 INTERVAL TIMERS (TIMER A, TIMER B)...................320 INPUT MODES..........................................322 BIT NAMES on READ-Register...........................322 BIT NAMES on WRITE-Register .........................322 Time of Day Clock.......................................323 BIT NAMES for WRITE TIME/ALARM or READ TIME..........323 Serial Shift Register (SDR).............................324