Supermicro SUPER P3TDE6/P3TDER — Supermicro SUPER P3TDE6/P3TDER Motherboard User Manual PDF

Preface Preface About This Manual This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the SUPER P3TDE6/P3TDER mainboard. The SUPER P3TDE6/P3TDER sup- port single or dual Pentium ® III 500 MHz-1.40 GHz FCPGA processors with a 512K L2 cache at a 133/100 MHz front side bus. Please refer to the support section of our web site (http://www.supermicro.com/ TechSupport.htm) for a complete listing of supported processors. Pentium III FCPGA (Flip Chip Pin Grid Array) processors are housed in a 370-pin socket, which is the standard that will support future Intel proces- sors.

The P3TDER has been optimized for use in 1U rackmount systems. Manual Organization Chapter 1 includes a checklist of what should be included in your mainboard box, describes the features, specifications and performance of the SUPER P3TDE6/P3TDER mainboard and provides detailed information about the chipset. Chapter 2 begins with instructions on handling static-sensitive devices. Read this chapter when you want to install the processor and DIMM memory modules and when mounting the mainboard in the chassis.

Also refer to this chapter to connect the floppy and hard disk drives, SCSI drives, the IDE interfaces, the parallel and serial ports and the twisted wires for the power supply, the reset button, the power LED, the speaker and the keyboard. Chapter 3 describes troubleshooting procedures for the video, the memory and the setup configuration stored in CMOS. For quick reference, a general FAQ section is provided. Instructions are also included for contacting tech- nical support. In addition, you can visit our web site at www.supermicro.com/techsupport.htm for more detailed information.

Chapter 4 includes an introduction to BIOS and provides detailed informa- tion on running the CMOS Setup utility. Appendix A gives information on BIOS error beep codes. Appendix B provides POST checkpoint codes. iii