The Z-8~A section contains an intelligent serial I/O controller circuitry that provides high speed data transfer to and from the user terminals. Within the Z-8~A section is the Z-8~A micro- processor, three Z-8~A SIO controllers for five channels, two timer devices and a small amount of RAM and ROM. 8~186 MICROPROCESSOR ARCHITECTURE This section describes the architecture of the 8~186 microproces- sor within the 486 system, specifically the addressing modes, the OMA function and programmable timers. Addressing Modes There are three addressing schemes done through the 8~186 in the 486 system: 1) operand addressing, 2) external port or register addressing, and 3) main memory addressing.
Memory addressing is discussed later in this chapter. Operand Addressing The 8~186 Microprocessor has eight operand addressing modes. Two addressing modes are provided for instructions that operate on internal register or immediate operands and six addressing modes are provided to specify the location of an operand in a memory segment. A memory operand address consists of two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either implicity chosen by the addressing mode or explicitly chosen by a segment override prefix. The offset is calculated by summing any combination of the following three address elements.
The displacement (an 8- or 16-bit immediate value contained in the instruction) The base (contents of either the BX or BP base registers) The index (contents of either the SI or 01 index registers) For more information on operand addressing modes, refer to the data book. Port and Register Addressing The port or register addresses are composed of a programmable base address and an offset. A list of these offset values are provided in Tables 5-1 through 5-19. 5-3