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ACKNOWLEDGEMENTS CP/M is a registered trademark of Digital Research, Inc. XENIX is a trademark of Microsoft Inc. UNIX is a trademark of Bell Laboratories FEDERAL COMMUNICATIIONS COMMISSION NOTICE WARNING This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions manual, may cause interference to radio communications. It has been tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment.
Operation of this equipment in a residential area is likely to cause interference in which case the user, at his own expense, will be required to take whatever measures may be required to correct the interference.
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Contents PAGE SUBJECT 1-1 1-1 1-3 1-3 1-3 1-3 1-4 1-4 1. SY~EII OVERVIEW FEATURES AND CAPABILITIES SYSTEM SOFTWARE OPERATING SYSTEMS SYSTEM MONITOR DIAGNOSTICS OPI'IONS RELATED DOCUMENTS 2-1 2-1 2-3 2-5 2-7 2. SPECIFICATIONS SYSTEM SPECIFICATIONS POWER SU PPL Y FLOPPY DISK DRIVE HARD DISK DRIVE 3-1 3-1 3-1 3-4 3. SYSTEM ARCBITEC'roRE INTRODUCTION BUS STRUCTURE MEMORY ARBITRATION 4-1 4-1 4-1 4-1 4-3 4-3 4-4 4-4 4-4 4-4 4. GENERAL SYSTEM FUNcrIONAL DESCRIPrION INTRODUCTION CPU BOARD 80186 MICROPROCESSOR MEMORY DEVICES MEMORY MANAGEMENT UNIT (MMU) FLOPPY DISK DRIVE WORKNET Z-80A I/O PROCESSOR HARD DISK CONTROLLER BOARD 5-1 5-1 5-1 5-3 5-3 5-4 5-6 5-7 5-12 5-13 5-23 5-24 5-24 5.
SUBSYSTEM FUNCTIONS INTRODUCT ION CENTRAL PROCESSING UNIT (CPU) HARDWARE OVERVIEW 80186 MICROPROCESSOR ARCHITECTURE Addressing Modes Direct Memory Access (DMA) Operation Programmable Timer Operation Interrupt Control Operation MEMORY ADDRESSING MEMORY MANAGEMENT UNIT SYSTEM CONTROL PORT FLOPPY DISK CONTROLLER OPERATION Programming
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TABLE OF CONrEftS PAGE SUBJECT 5-25 Z-80A I/O CONTROLLER 5-25 Functional Description 5-26 Z-80A I/O Processor Memory 5-27 80186/Z-80A Comrnunnications 5-28 Host/Controller Communication 5-28 Controller Initialization 5-29 Channel Initialization 5-29 Channel Transmit Operation 5-29 Channel TTY Receive Operation 5-29 Channel Ring Buffered Receive Operation 5-30 Modem Status Operation 5-30 REGISTER DEFINITIONS 5-30 Initialization Register 5-31 Control Registers 5-32 Communication Channel Registers 5-36 HARD DISK CONTROLLER HARDWARE OVERVIEW 5-36 INTRODUCTION 5-36 FUNCTIONAL DESCRIPTION 5-36 Disk Drive Description 5-36 Head Selection 5-39 Formatting Guidelines 6-1 6.
FIRMWARE IN'rERFACB 6-1 INTRODUCTION 6-1 SYSTEM MONITOR 6-3 Monitor Location 6-4 Debugger Program 6-5 Entering the Debugger Program 6-5 Executing a Debugger Command (An example) 6-12 486 Monitor's System Call Interface 6-18 Power-up Test 6-19 Power-up Test Error Reporting Scheme 6-19 Power-up Test Descriptions A-I APPENDIX A. 486 CPU JUMPlCR:mG SPECIFICATIONS B-1 APPENDIX B.
PORT CONNECTIONS ILLUS'l'RATIONS 1-2 Figure 1-1 Altos Model 486 Computer System 3-2 Figure 3-1 Bus Architecture 4-2 Figure 4-1 System Block Diagram 5-2 Figure 5-1 CPU Board Block Diagram 5-8 Figure 5-2 Master/Slave PIC Configuration 5-9 Figure 5-3 Interrupt Request 5-37 Figure 5-4 Hard Disk Controller Board Circuitry 5-40 Figure 5-5 Sector Format A-I Figure A-I CPU Jumper Locations B-5 Figure B-1 Hard Disk Drive
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TABLE OF CONrEftS PAGE SUBJECT TABLES 5-5 5-5 5-6 5-8 5-10 5-11 5-12 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Tabl e 5-7 Chip Select Register Offsets DMA Register Offsets Timer Control Register Offsets Interrupt Controller Register Offsets System Maskable Interrupts Master PIC Register Offsets 80186 Microprocessor Predefined Types and Default Priority System Memory Map Memory Management Relocation Register Violation Port Bits Control Port Address Offsets Control Bits PIA Port Address Offsets Floppy Disk Control Port Address Offsets Floppy Disk Controller Port Address Off sets Z80 Port Assignments SIOA Port Address Offsets SlOB Port Address Offsets 5-13 5-14 5-22 5-23 5-23 5-24 5-25 5-25 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 5-25 5-26 5-26 5-26 5-28 5-40 5-41 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20 Table 5-21 Table 5-22 Z-8~A Memory Addressing Internal Hard Disk Connectors Disk Data Format Conversion from Byte Offset to Sector Number Monitor Memory Map Debugger Support Commands Debugger's Command Syntax Monitor System Calls Peripheral I/O Parameter Block Layout Peripheral I/O Parameter Block Definition Power-up Test Structure Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 6-3 6-4 6-6 6-13 6-16 6-17 6-18
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