2 Functions of Devices in DVP-PLC DVP-PLC Application Manual 2-62 ES SA Off STOP RUN EH2 EH3 Special D Function EX SX Attribute Latched Default SV SV2 SS SC On RUN STOP D1199* SA/SX: When X3 interruption (I301) occurs, immediately extracting the high 16 byte from X1 high-speed counting value. (Only supports V1.8 and above versions.) SC: When X5 interruption (I501) occurs, extracting the high 16 byte from high-speed counting value. (Only supports V1.8 and above versions.) EH3/SV2: Enabling X3 to get the counting value of the high-speed counter C241 (M1058 is On) (High word) ╳ ○ ╳ ○ 0 0 - R NO 0 D1200* Start latched address for auxiliary relays M0 ~ M999 # -> EH2/EH3/SV2: 500; SA/SX/SC:
512 ╳ ○ ○ ○ - - - R/W YES # D1201* End latched address for auxiliary relays M0 ~ M999 ╳ ○ ○ ○ - - - R/W YES 999 D1202* Start latched address for auxiliary relays M2000 ~ M4095 ╳ ○ ○ ○ - - - R/W YES 2,000 D1203* End latched address for auxiliary relays M2000 ~ M4095 ╳ ○ ○ ○ - - - R/W YES 4,095 D1204* Start latched address for 100ms timers T0 ~ T199 ╳ ╳ ○ ○ - - - R/W YES H'FFFF D1205* End latched address for 100ms timers T0 ~ T199 ╳ ╳ ○ ○ - - - R/W YES H’FFFF D1206* Start latched address for 10ms timers T200 ~ T2 ╳ ╳ ○ ○ - - - R/W YES H’FFFF D1207* End latched address for 10ms timers T200 ~ T239 ╳ ╳ ○ ○ - - - R/W YES H’FFFF D1208* Start latched address for16-bit counters C0 ~ C199 # -> EH2/EH3/SV2:
100; SA/SX/SC: 96 ╳ ○ ○ ○ - - - R/W YES # D1209* End latched address for 16-bit counters C0 ~ C199 ╳ ○ ○ ○ - - - R/W YES 199 D1210* Start latched address for 32-bit counters C200 ~ C234 # -> EH2/EH3/SV2: 220; SA/SX/SC: 216 ╳ ○ ○ ○ - - - R/W YES # D1211* End latched address for 32-bit counters C200 ~ C234 ╳ ○ ○ ○ - - - R/W YES 234 D1212* Start latched address for 32-bit high-speed counters C235 ~ C255 ╳ ○ ○ ○ - - - R/W YES 235 D1213* End latched address for 32-bit high-speed counters C235 ~ C255 ╳ ○ ○ ○ - - - R/W YES 255 D1214* Start latched address for steps S0 ~ S899 # -> EH2/EH3/SV2: 500; SA/SX/SC: 512 ╳ ○ ○ ○ - - - R/W YES # D1215* End latched address for steps S0 ~ S899 # -> EH2/EH3/SV2:
899; SA/SX/SC: 895 ╳ ○ ○ ○ - - - R/W YES # D1216* Start latched address for registers D0 ~ D999 ╳ ○ ○ ○ - - - R/W YES 200 D1217* End latched address for registers D0 ~ D999 ╳ ○ ○ ○ - - - R/W YES 999 D1218* Start latched address for registers D2000 ~ D9999 ╳ ○ ○ ○ - - - R/W YES 2,000 D1219* End latched address for registers D2000 ~ D9999(# -> EH2/EH3/SV2: 11999; EH2: 9999; SA/SX/SC:
4999) ╳ ○ ○ ○ - - - R/W YES # D1220 Phase of the 1st group pulse output CH0 (Y0, Y1) ╳ SX V3.0 ○ ○ 0 - - R/W NO 0 D1221 Phase of the 2nd group pulse output CH1 (Y2, Y3) ╳ ╳ ○ ○ 0 - - R/W NO 0 D1222 Time difference between direction signal and pulse output for the 1st group pulse CH0 (Y0, Y1) in DRVI, DDRVI, DRVA, DDRVA, PLSV, DPLSV ╳ ╳ ○ ○ 0 - - R/W NO 0 D1223 Time difference between direction signal and pulse output for the 2nd group pulse CH1 (Y2, Y3) in DRVI, DDRVI, DRVA, DDRVA, PLSV, DPLSV ╳ ╳ ○ ○ 0 - - R/W NO 0 D1225 Counting mode of the counter HHSC0 ╳ ╳ ○ ○ 2 - - R/W NO 2