int e l APPENDIX B INSTRUCTION SET SUMMARY This appendix contains two tables (see tables B-1 and B-2): the first identifies all of the 8052's instructions in alphabetical order; the second table lists the instructions according to their hexadecimal opcodes and lists the assembly language instructions that produced that opcode. The alphabetical listing also includes documentation of the bit pattern, flags affected, number of machine cycles per execution and a description of the instructions operation and function. The list below defines the conventions used to identify operation and bit patterns.
ABBREVIATIONS AND NOTATIONS USED - 200 - A Accumulator AB Register Pair B Multiplication Register bit address 8052 bit address page address 11-bit code address within 2K page relative offset 8-bit 2's complement offset C Carry Flag code address Absolute code address data Immediate data data address On-chip 8-bit RAM address DPTR Data pointer PC Program Counter Rr Register (r = 0-7) SP Stack pointer High High order byte low Low order byte i-j Bits i through j .n Bit n aaa aaaaaaaa Absolute page address encoded in instruction and operand byte bbbbbbbb Bit address encoded in operand byte dddddddd Immediate data encoded in operand byte llllllll One byte of a 16-bit address encoded in operand byte mmmmmmmm Data address encoded in operand byte oooooooo Relative offset encoded in operand byte r or rrr Register identifier encoded in operand byte AND Logical AND NOT Logical complement OR Logical OR XOR Logical exclusive OR + Plus - Minus / Divide · Multiply (X) The contents of X ((X)) The memory location addressed by (X) (The contents of X) = Is equal to Is not equal to Is greater than