int e l Table B-1. Instruction Set Summary - 201 - Mnemonic Operation Cycles Binary Code Flags P OV AC C Function ACALL code addr (PC) 2 a a a 1 0 0 0 1 a a a a a a a a Push PC on stack, and replace low order 11 bits with low order 11 bits of code address. ADD A,#data (A) 1 0 0 1 0 0 1 0 0 d d d d d d d d P OV AC C Add immediate data to A. ADD A,@Rr (A) 1 0 0 1 0 0 1 1 r P OV AC C Add contents of indirect address to A. ADD A,Rr (A) 1 0 0 1 0 1 r r r P OV AC C Add register to A. ADD A,data addr (A) 1 0 0 1 0 0 1 0 1 m m m m m m m m P OV AC C Add contents of data address to A.
ADDC A,#data (A) 1 0 0 1 1 0 1 0 0 d d d d d d d d P OV AC C Add C and immediate data to A ADDC A,@Rr (A) 1 0 0 1 1 0 1 1 r P OV AC C Add C and contents of indirect address to A. ADDC A,Rr (A) 1 0 0 1 1 1 r r r P OV AC C Add C and register to A ADDC A,data addr (A) 1 0 0 1 1 0 1 0 1 m m m m m m m m P OV AC C Add C and contents of data address to A AJMP code addr (PC) 0-10 2 a a a 0 0 0 0 1 a a a a a a a a Replace low order 11 bits of PC with low order 11 bits code address. ANL A,#data (A) 1 0 1 0 1 0 1 0 0 d d d d d d d d P Logical AND immediate data to A.
ANL A,@Rr (A) 1 0 1 0 1 0 1 1 r P Logical AND contents of indirect address to A ANL A,Rr (A) 1 0 1 0 1 1 r r r P Logical AND register to A ANL A,data addr (A) 1 0 1 0 1 0 1 0 1 m m m m m m m m P Logical AND contents of data address to A. ANL C,bit addr (C) 2 1 0 0 0 0 0 1 0 b b b b b b b b C Logical AND bit to C ANL C,lbit addr (C) 2 1 0 1 1 0 0 0 0 b b b b b b b b C Logical AND complement of bit to C ANL data addr, #data (data address) 2 0 1 0 1 0 0 1 1 m m m m m m m m d d d d d d d d Logical AND immediate data to contents of data address ANL data addr,A (data address) 1 0 1 0 1 0 0 1 0 m m m m m m m m Logical AND A to contents of data address.