AH500 Module Manual Note: D1000 and D500 in the above window are the registers in an AH500 series CPU module on the left of AH10DNET-5A functioning as a slave. The following figure illustrates the corresponding relations in the mapping areas of the master and slave. The master and slave both consist of AH10DNET-5A and an AH500 series CPU module. (AH500 + AH10DNET-5A) Master DeviceNet (AH500 + AH10DNET-5A) Slave Note: In the above figure, the maximum data length is introduced. But the actually configured data length may be different from it. 10-16 D505~ D999 D1005~ D1499