Chapter 1 Introduction With ISPSoft, users can choose different programming languages (instruction lists (IL), structured texts (ST), ladder diagrams (LD), sequential function charts (SFC), and Users can create an AH500 hardware function block diagrams (FBD) dealt with by IEC 61131-3 according to their needs when writing program. configuration by means of the hardware configuration software. 1.3 Characteristics 1. High efficiency AH500 basic series CPU module: A 32-bit high-speed processor is used. The instructions are executed at a speed of 3K steps/ms.
(Fifty percent of the instructions are basic instructions, and fifty percent of the instructions are applied instructions.) AH500 advance series CPU module: A 32-bit high-speed processor is used. The instructions are executed at a speed of 12K steps/ms. (Fifty percent of the instructions are basic instructions, and fifty percent of the instructions are applied instructions.) 2. Supporting more inputs and outputs The AH500 series CPU module supports up to 4,352 local digital I/O or 544 analog I/O. A complete AH500 system consists of eight backplanes at most, including a main backplane.
Twelve I/O modules at most can be installed on a main backplane, and eight I/O modules at most can be installed on an extension backplane. Therefore, for the AH500 series CPU, sixty-eight digital input/output modules at most or sixty-eight analog input/output modules at most can be installed. Eight RTU modules at most can be installed on the main backplane. ．．． Remote I/O 7 backplanes ｝ ｝ ． ． ． ． ． ． ． ． ． ． ． ． 7 backplanes 1-9