1-7. IC9 XC2S100-5TQ144C ( Field Programmable Gate Arrays (FPGA)) IDE controller. DMA controller between Voice-LSI and IDE/SCSI. MIDI interface. 1-7-2. Pin Descriptions SERVICE MANUAL 23 Signal name Dir Explanation /FP2 PROG _ out For configuration to FPGA on ADAT PCB. PLD2 TMS _ PLD2 TDI _ out For configuration to CPLD on DIO. PLD2 TDO _ in For configuration to CPLD on DIO. TCK,TMS,TDI in For configuration.(TCK is also used for CPLD on DIO) TDO out For configuration. VCCINT - Positive supply for internal logic. +3.3V VccIO - Positive supply for output driver. +3.3V GND - Ground supply. Signal name Dir Explanation CD[15:0] i/o Connected with CPU bus for communication.
A[5:0] in Connected with CPU address bus for communication. /IDE CS _ in Chip select for this FPGA. /CPU RD _ in Data output enable of CPU bus. /CPU WR _ in Data strobe of CPU bus. RESET in Initialize FPGA logic. Active high. LSI D[15:0] _ i/o Connected with DMA data bus of Voice-LSI. IDE D[15:0] _ i/o Connected with data bus of IDE. IDE DA[2:0] _ out Connected with DA[2:0] of IDE I/F /IDE CS1,0 _ out Connected with CS[1:0] of IDE I/F. /IDE IORD _ Out Connected with /DIOR HD of IDE I/F. _ /IDE DIOW _ Out Connected with /DIOW STOP of IDE I/F. _ IORDY in Connected with IORDY of IDE I/F. /IDE DMACK _ out Connected with /DMACK of IDE I/F. IDE DMARQ _ in Connected with DMARQ of IDE I/F.
CPU RDY _ out Connected with CPU RDY. SCSI DMAREQ _ in Connected with SCSI controller. DMA control. /SCSI DMACK _ out Connected with SCSI controller. DMA control. LSI DMAREQ _ out Connected with Voice-LSI. DMA control. /LSI DMAACK _ in Connected with Voice-LSI. DMA control. /LSI DMARD _ in Connected with Voice-LSI. DMA control. /LSI DMAWR _ in Connected with Voice-LSI. DMA control. /INT DMA _ out Interrupt request output of DMA to CPU. Active low. LRCK in Word clock of system. Connected with Voice-LSI. SFrame out Pin No.133. Frequency= Fs/256. duty cycle= 255:1. MIDI IN1,2 _ in MIDI 2 input. MIDI OUT1-4 _ out MIDI 4 output. /INT MIDI _ out Interrupt request output of Midi to CPU. Active low.
MCLK in Master clock of FPGA logic. CCLK in Configuration clock I/O pin. /INIT i/o For configuration. Active Low. /PROGRAM in Initiates a configuration sequence when asserted Low. DONE i/o Indicates that configuration is complete. open drain. M0,M1,M2 in configuration mode pin. TCK,TMS,TDI in # Not used though this is connected # VCCINT - Power supply for internal core logic. +2.5V VccO - Power supply for output driver. +3.3V GND - Ground supply.