4) Byte transfer with both source and destination pointers remaining the same.* 5) Word transfer with both source and destination pointers decremented.* 6) Byte transfer with both source and destination pointers decrement. * *Refer also to DMA source and destination register offsets in Chapter 5. In each case, a background pattern is written in the destination area. Also, a wait loop is used to check the CPU's DMA counting ability. An error is reported if either the wait-time expires or the background pattern remains unchanged. 15) Diag-console Controller (8274) test - Two patterns (number 0000 and number ffff (hex» are used to check for the RS232 interface.
The port address is at serial I/O channel A-12a6 (hex). 16) Floppy Controller (765) Test - Since sending a command to the floppy controller requires several read and write operations, the Monitor verifies the floppy interface by sending a specify command. This specify command tells the controller about the drive's characteristics. If the controller accepts the command, this test is passed. 17) Memory Parity Test - Two patterns of Number 0000 (even parity) and Number fefe (hex) (odd parity) are used to check the memory parity generating logic. First, the NMI vector, parity service routine, and parity generating circuit are programmed and enabled.
Next, location Number 7000(hex) of every segment is written and read back with the data patterns. If there is a parity error, the parity service routine sets the error flag. 6-23