To obtain the physical address for a port or an external register, the offset address is added to the base address. The base address refers to a particular address range in the I/O space. For example, if the base address were programmed to start at 1000 and if the floppy status register were being addressed, the offset address, 280 (hex), would be added to the base address, and the result would be 1280 (hex). NOTE The default base address in this system is 1000. The starting address is defined by the PACS register of the 80186 as programmed by the user. For more information on programming the PACS register, refer to the data book.
Pheripheral chip select lines, PCS0* through PCS3*, on the 80186 chip are used to select this starting address range block in the I/O space, PCS0* enables block 1000, PCS1* enables block 2000 and so forth. See the internal PCS register offsets in Table 5-1. An MPCS register determines the mode of operation of the peripheral chip selects. Refer to the data book for more information on this function. NOTE Do not confuse a register or port address offset with a memory offset. A memory offset is used to construct the 20 bit address. Refer to discussions on Bus Structure in Chapter 3 and Memory Addressing later in this chapter.
Direct Memory Access (DMA) Operation Direct Memory Access (DMA) can be instructed, by the Hard Disk Drive Controller printed circuit board, the Floppy Disk Drive Controller chip or the WorkNet, to access the full contents of main memory. Data can be transferred directly from memory to I/O, memory to memory, or I/O to I/O, without the intervention of the microprocessor. This leaves the mircroprocessor free for other tasks. The 80186 microprocessor provides two independent high-speed DMA channels. Each channel has six registers in the control block that define that channel's specific operation, see Table 5-1.
The control registers consist of a 20-bit source pointer, a 20- bit destination pointer, a 16-bit transfer counter and a 16-bit control word. Data may be transferred in eight bit or sixteen bit transfers. 5-4