Interrupt Control Operation Internal and external interrupts provide a means of stopping the normal processing flow in order to handle unexpected or difficult situations. The system operates in the RMX Mode and requires an external master Programmable Interrupt Controller (PIC), the Intel 8259, to handle and service interrupts. As stated earlier, the 8~186 contains a built-in PIC which acts as a slave to the external PIC. The internal 8~186 resources will be monitored through the internal interrupt controller. See Figure 5-2 for a block diagram of the master/slave PIC setup.
When an internal interrupt takes place, the internal slave Interrupt Controller, residing in the 8~186 Microprocessor, resolves priorities and generates an internal interrupt request to the external master PIC. Internal interrupts are from Timers and DMA channels and can be disabled by their own control regis- ters or by mask bits within the interrupt controller. There are 15 registers in the internal peripheral control block, see Table 5-4@ The external master PIC resolves priorities among all the external interrupt sources and issues an interrupt to the 8~186 Microprocessor. The 8~186 Microprocessor then causes an interrupt acknowledge cycle to take place.
After the interrupt condition is serviced the system continues with the user program. Five pins on the 8~186 are dedicated for the interrupt function: NMI - Non-Maskable Interrupt is typically used for parity errors or a reset. INT~ - Input is used as the 186 cre interrupt. INTI - Input is used as a slave select input. INT2 - Output is used as an acknowledge output. INT3 - Output is to the PIC. There are eight different levels of system interrupts, interpreted by the PIC, (in order of importance to the system.) The lower the Bit Designation Number is, the more important the interrupt. Therefore, all Memory Mangagement Interrupts are handled before all I/O Port Interrupts.
Table 5-5 lists the interrupts in numeric order (and order of importance.) Figure 5- 3 illustrates the interrupt activity which are discussed briefly in the following paragraphs. 5-7