SYSTEM CONTROL PORT The system control decoder port (See Table 5-11) is a decoder PAL (Programable Array Logic) chip which performs some important tasks for the system. This port does the following: 1) Enables the output of an MMU PAL (through the "read violation" command) so that memory cycles can take place. 2) Clocks a flip flop to enable the system to read critical control bits, (See Tables 5-11 and 5-12) at ~l~ control bits register. 3) Sets up a timer interrupt to the external PIC, See Table 5-11 for register information.
Table 5-11 Control Port Address Offsets I ADDRESS (HEX) 1 FUNCT ION 1 1------------------------------------------1 1 292H 1 READ VIOLATION PORT 1 I 296H 1 CONTROL BITS REG 1 1 298H 1 CLRTlMER INT 1 1-----------------1------------------------1 Table 5-12 Control Bits 1 BIT NO. I FUNCl' ION 1 3 Clear Parity Error* 1 4 Req ue st User Mode I 7 Clear Violation Port* 1 14 Clear Memory Management Unit* 1 1-------------------------------------------1 1 *Active low. 1 8255A PERIPHERAL INTERFACE ADAPTER (PIA) The 8255A is a three-port general-purpose I/O device that performs the following functions. 1) Interfaces the floppy drive circuitry to the data and LA buses.
2) Provides a non-maskable interrupt (channel attention) signal to the Z-80A I/O processor. 3) Supplies maskable interrupts to the 80186 section from various sources. There are three types of registers within the 8255A, data, control and status along with three 8-bit I/O ports (A, B and C). Port addresses for these registers are supplied in Table 5-13. 5-23