=12 4800 bps =13 7200 bps =14 9600 bps =15 19.2 kbps bit 12 unused bit 13 unused bit 14 CTS control bit 15 DSR control Channel Status Register The channel status register is a 16-bit register containing the following information:
bit 0 transmitter empty bit 1 Data Terminal Ready bit 2 not used bit 3 Request To Send bit 4 parity error bit 5 receive data lost (SIO overrun) bit 6 framing error bit 7 parity OR overrun OR framing error bit 8 receive character(s) ready bit 9 unused - always 0 bit 10 unused - always 0 bit 11 unused - always 0 bit 12 transmitter ready/-active bit 13 unused - always 0 bit 14 unused - always 0 bit 15 unused - always 0 Channel Command Register The channel command register is an 8-bit register used to pass commands to the controller. Bit 7 is used to indicate the exis- tence of a valid command. The host should test bit 7 to insure that the last command has been executed.
The controller will clear bit 7 after reading the command. At this time, the four least significant bits will also be cleared, while bits 4-6 will retain their values. Bits 4-6 contain the logic level correspon- ding to the interrupt enable status. The commands available are: o no operation 1 initialize channel 2 start transmitter 3 acknowledge receiver 4 abort transmitter 5 reserved 6 "Break" control 7 not used 5-33