1 Basic Principles of PLC Ladder Diagram Example 11: Delay circuit X0 X0 Y1 T10 Y1 Time base: T = 0.1 sec 100 seconds When input X0 is On, due to that its corresponding normally closed contact is Off, time T10 will be Off and the output coil Y1 will be On. T10 will be On and start to count until input X0 is Off. Output coil Y1 will be delayed for 100 seconds (K1,000 Ч 0.1 sec = 100 secs) and be Off. See the timing diagram above. Example 12: Output delay circuit The output delay circuit is the circuit composed of two timers. When input X0 is On and Off, output Y4 will be delayed. X0 T5 Y4 T6 Y4 Y4 Example13:
Timing extension circuit X0 The total delay time from input X0 is closed to output T11 Y1 is On = (n1+n2)* T. T refers to the clock cycle. T12 X0 T11 n1* T Timer = T11, T12 n2* T Clock cycle: T T12 Y1 (n1+n2)* T DVP-PLC Application Manual 1-21 TMR T10 K1000 5 6 5 secs T 3 secs TMR T5 K50 TMR T6 K30 TMR T11 Kn1 TMR T12 Kn2 Y1