8 Application Instructions API 100-149 API 148 Operands: m : Address in the file register to be read D : Device for storing the read data (starting from the designated D) n : Number of data read at a time Explanations: 1. Range of m : K0 ~ K1,599 (SA/SX/SC); K0 ~ K9,999 (EH/EH3); K0~49999 (EH3 V1.4/SV2 V1.2 (and above)) 2. Range of D : D2000 ~ D4999 (SA/SX/SC); D2000 ~ D9999 (SX V3.0 and above); D2000 ~ D9999 (EH); D2000~D11999 (EH3/SV2) 3. Range of n : For 16-bit instruction K1 ~ K1,600 (SA/SX/SC), K1 ~ K8,000 (EH/EH3/SV2); For 32-bit instruction K1 ~ K800 (SA/SX/SC), K1 ~ K4,000 (EH/EH3/SV2) 4. See the specifications of each model for their range of use. 5. Flag: M1101.
See explanations below. 6. SA/SX/SC/EH/EH2/SV/EH3/SV 2 uses this instruction to read the data in file registers and store them into data registers. 7. SA/SX/SC offers 1,600 16-bit file registers. 8. m and n of SA/SX/SC do not support E and F index register modification. 9. EH/EH2/SV/EH3/SV2 is equipped with 10,000 16-bit file registers (number 0~number 9999). EH3 V1.40 abd above/SV2 V1.20 and above are equipped with 50,000 file registers. The 40,000 file registers added are number 10,000~number 49,999. The 40,000 file registers are stored in the flash ROM. It is suggested that data should be written into the 40,000 file registers by means of WPLSoft or ISPSoft. 10.
If m , D and n fall without their range, operation error will occur. M1067, M1068 = On and D1067 will record the error code H’0E1A. Program Example 1: 1. The 16-bit instruction MEMR reads 100 data at address 10 in the file register and store the read data in register D starting from D2000. 2. When X0 = On, the instruction will be executed. When X0 = Off, the instruction will not be executed and the previously read data will remain unchanged. X0 DVP-PLC Application Manual 8-71 Mnemonic Operands Function D MEMR P Read File Register Type OP Bit Devices Word Devices Program Steps X Y M S K H KnX KnY KnM KnS T C D E F MEMR, MEMRP: 7 steps DMEMR, DMEMRP:
13 steps m * * * D * n * * * PULSE 16-bit 32-bit EH3 SV2 ES EX SS EH3 ES EX SS EH3 ES EX SS SA SX SC EH SV SA SX SC EH SV SA SX SC EH SV SV2 SV2 MEMR K10 D2000 K100