int e l 8.3 IMPLEMENTING "FAKE DMA" The MCS BASIC-52 device does not contain an hardware mechanism that supports Direct Memory Access (DMA). However, the DMA function is supported in software by MCS BASIC-52. During DMA operation MCS BASIC-52 guarantees that no external memory access will be performed. To enable the DMA function, the following must be performed: 1) BIT 49, which is located in internal memory location 38.1 (26.1H) must be set to a one. This can be accomplished in BASIC by using the statement -- DBY(38) = DBY(38).0R.02H 2) BIT 0 and BIT 7 of the SPECIAL FUNCTION REGISTER, IE (Interrupt enable) must be set to a one.
This can be accomplished in BASIC by using the statement -- IE = IE.OR.81H After the three BITS mentioned above are set to a one, external interrupt zero (/INT0) acts as a DMA input pin. /INT0 is pin 12 on the 8052AH. Whenever /INT0 is pulled low (to a logical zero state), the MCS BASIC-52 device will enter the DMA mode and no accesses will be made to external memory. To acknowledge that MCS BASIC-52 has entered the DMA mode, MCS BASIC-52 outputs a zero on pin 7 (P1.6). In essence, PORT 1.6 is the /DMA ACK pin of the MCS BASIC-52 device.
In most applications, this pin would be used to disable three-state buffers that would be placed on PORT2, PORT0, and the address latch of the MCS BASIC-52 system. After the user pulls the /INT0 pin high, MCS BASIC-52 will output a one on P1.6 and normal program execution will continue. During this "fake DMA" cycle, the MCS BASIC-52 program does nothing except wait for the /INT0 pin to be pulled high. So, program execution is halted. It should be noted that although this "fake DMA" operation does provide the same functionality as a normal DMA hardware mechanism, it also takes substantially longer for the normal DMA REQUEST -- DMA ACKNOWLEDGE cycle to be performed.
That is because MCS BASIC-52 uses interrupts to implement the DMA operation, instead of dedicated hardware. As a general rule, cycle stealing DMA is not an option with MCS BASlC-52's "fake" DMA. Only "burst mode" DMA cycles can be implemented without a significant time penalty. When "fake DMA" is implemented, the user must provide three-state buffers on the PORT2, PORT0, and the address latch of the MCS BASIC-52 system. - 101 -