User Manual of EM760 High-Performance Inverter 286 F02.14 Reserved 0 × 0x020E 21: Acceleration and deceleration prohibition 22: operation pause 23: external fault input 24: Switching of RUN command to keyboard 25: switching of RUN command to communication 26: Frequency source switching 27: clearing of regular running time 28: speed control/torque control switching 29: torque control prohibition 30: motor 1/motor 2 switching 31: resetting of simple PLC status (running from the first segment, with the running time cleared) 32: simple PLC time pause (keep running at current segment) 33: Zero-servo command 34: counter input (≤250Hz) 35: high-speed count input (≤100kHz, only valid for X7) 36:
count clearing 37: length counter input (≤250Hz) 38: High-speed length counting input (≤100kHz, only valid for X7) 39: length clearing 40: pulse input (≤ 100 kHz,only valid for X7) 41: process PID pause 42: process PID integral pause 43: PID parameter switching 44: PID positive/negative switching 45: stop and DC braking 46: DC braking at stop 47: immediate DC braking 48: fastest deceleration to stop 50: external stop 51: switching of main frequency source to digital frequency setting 52: switching of main frequency source to AI1 53: Switching of main frequency source to AI2 54: switching of main frequency source to AI3 55: Switching of main frequency source to high- frequency pulse input 56:
switching of main frequency source to communication setting 57: inverter enabling 69: Reserving prohibited xor 89: Reset feedforward 121: External material cutoff signal 122: Wiring detection signal 123: Brake reset terminal F02.15 Positive/negative logic 1 of digital input terminal D7 D6 D5 D 4 D3 D2 D1 D0 *0000000 O 0x020F * X7 X6 X 5 X4 X3 X2 X1 0: positive logic is valid in the closed state/invalid in the open state 1: negative logic is valid in the closed state/invalid in the open state F02.16 Positive/negative logic 2 of digital input terminal D7 D6 D5 D 4 D3 D2 D1 D0 00000000 O 0x0210 X11 X1 0 X9 X 8 AI4 AI3 AI2 AI1 0:
positive logic is valid in the closed state/invalid in the open state 1: negative logic is valid in the closed state/invalid in the open state