Chapter 8 Serial Communication Module AH10SCM Mapping register: Users can select an internal register in AH10SCM-5A, or a register in a CPU module. I1, I2, O1, and, O2 are internal registers in AH10SCM-5A. For a CPU module, D Register or Base+Offset can be selected. Length Class: Users can select 1 Byte or 2 Bytes in the Class box. Format: Users can select Hex or ASCII in the Format box. Value: Users can enter a length. Checksum Class: Users can select a class. Format: Users can select the format of a checksum Initial value: Users can set an initial value. Reverse: The high byte of a one-word checksum which is calculated, and the low byte of the checksum are reversed.
8.6.3.2 Command After several TX packets and RX packets are created, users can select packets which will be sent and packets which will be received by creating commands. Besides, the users can set the sequence of executing the commands. Command number: Every command is numbered. Command numbers indicate execution sequence. Command type: Users can select Send , Receive , or Send & Receive in the Command Type box. Send packet: Users can select a packet which has been created. Receive packet: Users can select a packet which has been created. Success: Users can specify an action which follows the execution of a command. They can select Next , Goto , or End . Next: The next command is executed.
If the command which is being executed is command 1, the next command which will be executed is command 2. Goto: Users can specify a command which should be executed much later. 8-31 Register Definition Register Definition D Internal data register in a CPU module Base+Offset Used with a control register I1 Used for the receiving/sending of data through COM1 O1 Used for the sending of data through COM1 I2 Used for the receiving/sending of data through COM2 O2 Used for the sending of data through COM2