The 8~186 requires a 2~-bit address to access all the possible locations in main memory; a 16-bit address can only access 65,536 bytes of memory. The processor creates this 2~-bit address by appending four low order zeros (A0 through A3) to the 16-bit segment address (which specifies a 64K segment of memory) and combining this with a 16-bit offset address (which specifies a location within the segment). This 2~-bit bus is called the logical address (LA) bus. The LA Bus is created from the AD Bus when the addresses are 1 atched at ALE time and hel d for the entire bus cycl e. The boot and diagnostic PROM are addressed via the LA bus. When the LA bus is buffered, the XLA bus is developed.
The XLA bus provides virtual memory capability through relocation registers residing between the bus and the main memory. This means that if the data ,during a DMA transfer, is not in physical memory location it will be transferred into memory from the disk by the relocation registers addressing space process. The CPU board design is divided into two major hardware sections, the 8~186 section and the Z80 section. The XLA Bus connects these two major sections together so that either processor can access the main memory. The BD Bus is within the 8~186 section, it is the (Buffered) Bus which is created from the multiplexed AD Bus. The BD Bus is an I/O bus.
All devices which are in the I/O space of the 80186 processor send and receive data on this bus. The Mapped Address Bus is created through the Memory Management Unit (MMU). One function of the MMU is to create page addressing to memory. Another function of the Memory Management Unit is to protect the operating system from normal user access. Within the Z8~ section is the ZD~-7 (Data) Bus which is used by the Z80 Microprocessor to transfer eight data bits from the SIO ports to main memory and the 186 through the MD (Memory Data bus) Located on the ZD0-7 Bus are the SIO controllers for the five RS232 channels, two timer devices and a small amount of RAM and ROM.
The Z8~ address bus is used to access locations in the local 2K of RAM, for transferring instruction codes from the local control ROM and to interface the XLA bus for Z8~ I/O processing. 3-3