MEMORY ARBITRATION These are all the buses for the 486 system. You will note that both the Z8~ and 8~186 processors require main memory access. To allow both the Z8~ and 8~186 buses to share main memory, a cen- tral arbitration unit is used. This arbitration unit controls access to main memory. The central arbitration unit is a three way arbiter - arbitrating requests between the 186 and Z8~ and a refresh cycle. When a memory cycle has been allowed access to the bus, that request will be the only one serviced on the bus. A requesting memory cycle cannot interrupt a currently executing cycle. A refresh cycle must take place at lease every 15.6 us to recharge the dynamic RAM chips.
If all three requests arrive at the central arbiter at the same time, the refresh cycle has highest priority and the 8~186 cycle has second priority. Lower priority requests are cued and later executed.