9 Application Instructions API 150-199 API 168 Operands: S 1 : Source device 1 S 2 : Bits to be masked (OFF) D : Source device 2 / Operation results [ D = ( S 1 & S 2 ) | ( D & ~ S 2 )] Explanations: 4. The instruction conducts logical AND operation between S 1 and S 2 first, logical AND operation between D and ~ S 2 secondly, and combines the 1 st and 2 nd results in D by logical OR operation. 5. Rule of Logical AND operation: 0 AND 1 = 0, 1 AND 0 = 0, 0 AND 0 = 0, 1 AND 1 = 1 6. Rule of Logical OR operation: 0 OR 1= 1, 1 OR 0 = 1, 0 OR 0 = 0, 1 OR 1 = 1. 7. Among the SX models, only SX V3.0 and above are supported by the 32-bit instruction. Program Example 1:
When X0 = ON, MVM instruction conducts logical AND operation between 16-bit register D0 and H’FF00 first, logical AND operation between D4 and H’00FF secondly, and combines the 1 st and 2 nd results in D4 by logical OR operation. X0 D4 b15 b0 b15 b0 D4=H1234 執行前 D0=HAA55 AND AND HFF00 H00FF HAA00 H0034 OR 執行後 D4=HAA34 1 Program Example 2: Simplify instructions: X0 X0 = DVP-PLC Application Manual 9-76 Mnemonic Operands Function D MVM P Move the Designated Bit Type OP Bit Devices Word devices Program Steps X Y M S K H KnX KnY Kn M KnS T C D E F MVM, MVMP: 7 steps DMVM,DMVMP:
13 steps S 1 * * * * * * * * * S 2 * * * * * * * * * * * D * * * * * * * * * PULSE 16-bit 32-bit S SA SX SC EH SV EH3 SV2 ES EX SS SA SX SC EH SV EH3 SV2 ES EX SS SA SC EH3 ES EX S SX EH SV SV2 MVM D 0 H F F 00 1 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 WAND HFF00 D110 D110 MVM D 1 1 0 H F F 00 D120 WAND H00FF D120 D120 WOR D100 D120 D120