int e l 1.11 8052AH SPECIAL FUNCTION REGISTERS where SM0, SM1 specify the serial port mode, as follows: SM0 SM1 Mode Description Baud Rate 0 0 0 shift fosc /12 0 1 1 register variable 1 0 2 8-bit UART fosc./64 9-bit UART or fosc /32 1 1 3 9-bit UART variable SCON: Serial Port Control Register TCON: Timer/Counter Control Register (MSB) (LSB) TB8 is the 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. TI is transmit interrupt flag.
Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. SM2 enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. RI is receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN enables serial reception. Set by software to enable reception. Clear by software to dis- able reception. (MSB) (LSB) 0 1 0 1 0 1 0 0 Symb. Position Name and Significance Symb. Position Name and Significance TF1 TCON.7 Timer 1 overflow Flag. Set by hard- ware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 TCON.6 Timer 1 Run control bit. Set cleared by software to turn timer/ counter on/off. TF0 TCON.5 Timer 0 overflow flag. Set by hard- ware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR0 TCON.4 Timer 0 Run control bit. Set cleared by software to turn timer/ counter on/off.
IE1 TCON.3 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT1 TCON.2 Interrupt 1 Type control bit. Set cleared by software to specify falling edge/low level triggered external interrupts. IE0 TCON.1 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0 TCON.0 Interrupt 0 Type control bit. Set/ cleared by software to specify falling edge/low level triggered external interrupts. - 197 - SM0 SM1 SM2 REN TB8 RB8 TI RI TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0