S UPER S ERVER 6011D User's Manual Chipset The P3TDDR is based on the VIA Apollo Pro 266T chipset, which is a high- performance core logic chipset that consists of VIA's Apollo Pro266 chipset consists of two major components: the VT8633 V-Link Memory Host System Controller(North-bridge) and the VT8233 V-Link Client PCI/LPC Controller (South-bridge). The VIA Apollo Pro266 chipset is a high performance, cost-effective and energy efficient chipset for the implementation of AGP/V-Link/PCI/LPC com- puter systems based on 64-bit, 370 Pentium III (66 MHz/100MHz/133MHz), processors.
The VT8633 Host System Controller provides superior performance be- tween the CPU, DIMM, AGP bus, and V-Link inferface with pipelined, burst, and concurrent operation. The VT8233 V-Link Client Controller is a highly integrated PCI/LPC controller. Its internal bus structure is based on 33MHz PCI bus. The VT8233 integrated Clint V-Link Controller, which supports 266 MB bandwidth between Host/Client V-Link interface, provides a V-Link PCI and V-Link LPC controller. It supports three PCI slots arbitration and decod- ing for all integrated functions and LPC bus.
Processors The P3TDDR supports single or dual Pentium ® III FCPGA 500 MHz to 1.40 GHz and faster processors with a 512K L2 cache and single or dual low power Pentium ® III processors at front side bus speeds of 133 and 100 MHz. Please refer to the support section of our web site for a complete listing of supported processors: (http://www.supermicro.com/TechSupport.htm). Memory The P3TDDR has 4 DIMM slots that support up to 4 GB of ECC registered PC266 or PC200 DDR SDRAM. PC266 memory modules will run at full speed (266 MHz) in three slots only. If four slots are populated with PC266, memory will run at 200 MHz.
Module sizes of 128MB, 256MB, 512MB and 1 GB may be used to populate the DIMM slots. The DIMM slots are situated at a 25 degree angle to create a low profile and to promote efficient airflow through the chassis. It is not recommended that system memory speeds be mixed -- doing so will result in the memory operating at the slower speed. 1-4