Prior ity Resol ver This logic block determines the user-defined priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during INTA* pulse. The Interrupt Mask Register (IMR) allows the user to prevent (mask) an interrupt. During a particular application, if the parity failure interrupt occurs, it can be ignored. The mask allows the user to state at a given time which of those inter- rupts, listed in Table 5-5 is going to be accepted.
Table 5-5 Systea Maskable Interrupts IMn~aonic 1 Description 1 Bit 1 I I Designation 1---------------1-----------------------·-------1---------------- 1 MMINT 1 MEMORY MANAGEMENT INTERRUPI' I IR0 1 I NOT USED I IRl IAINT 1 ALTOSNET INTERRUPI' I IR2 1 INTRQ I INTERRU PT REQUEST I IR3 IINTERNAL INT 1 CPU INTERNAL INTERRUPI' 1 IR4 I 1 NOT USED 1 IR5 1 IOPINT I ZD0-7 BUS INTERRUPI' I IR6 ITMRINT I TIMING INTERRU PI' I IR7 1----------------------------------------------------------- Master PIC Operation When the Altos 486 Computer System is powered up, the CPU loads the initialization command word and operation command word into the PIC's internal registers, see Table 5-6.
The initialization command word provides the starting address of the service routines, while the operation command word provides the mode of operation. This mode is described below: Fully Nested Mode - After the initialization sequence IR0 has the highest priority and IR7 the lowest. This mode permits the PIC to operate as described above. The commands initially entered in the PIC internal registers are instructions which include what mode to enter and use. The initial command instructions can be permanently loaded in the PIC internal registers so that it will always operate in the same mode, or the loading instructions can be modified as conditions change by reprogramming the device.
Every interrupt is assigned a type code that identifies it. A table containing up to 256 pointers defines the proper interrupt 5-11