NOTES: *1. These are generated as the result of an instruction execution. **2. Generated by the Single-Step flag bit TF in the status word. Once this bit is set, an internal single step interrupt will occur after the next instruction has been executed. The interrupt clears the TF bit and uses an internally supplied vector of 1. The IRET instruction is used to set the TF bit and transfer control to the next instruction to be single-stepped. ****3. All three timers constitute one source of request to the interrupt controller. Among the timer interrupts, priority 2A is higher priority than 2B and 2B is higher than 2C. Each Timer interrupt has a separate vector type number. 4.
Default priorities for the interrupt sources are used only if you do not program each source into a unique priority level. ***5. The escape opcode (part of the instruction word that designates the function performed by a given instruction) will cause a trap only if the proper bit is set in the peripheral control block relocation register. MEMORY ADDRESSING Memory is addressed by a two component address, consisting of a l6-bit base segment and a l6-bit offset value, derived from a combination of pointer registers, instruction pointer, and immediate values. The l6-bit base values are contained in the one of four internal segment registers.
The physical address is calculated by shifting the base value LEFT by four bits and adding the l6-bit offset value to yield a 20-bit physical address. This allows the 80186 to access up to 1 Mbyte of physical main memory, if it were available for the system. With expansion memory, the 486 system can hold up to 896 Kbytes of main memory. 512 Kbytes is contained in the standard configuration. Table 5-8 shows a memory map of the system. 5-12