Table 5-17 SIOA Port Address Offsets ADDRESS (HEX) 1 FUNCl'ION 2AriJH 2A2H 2A4H 2A6H CH. A DATA CH. B DATA CH. A STATUS/COMMAND CH. B STATUS/COMMAND Table 5-18 SIOB Port Address Offsets 1 ADDRESS (HEX) 1 FUNCTION -------------------------------------------- 1 2BriJH CH. A DATA 1 2B2H CH. B DATA 1 2B4H CH. A STATUS/COMMAND 1 2B6H CH. B STATUS/COMMAND Z-81 I/O Processor Meaory The Z-8riJ's 64K of memory space is divided into two halves. The upper 32K is mapped into the system memory and the lower 32K is mapped into the local EPROM and Static RAM. The Z-8riJ can access the full contents of main memory but must do so in blocks of 32K bytes each.
The Z-8riJ loads the block number register before accessing system memory. When the system memory is accessed, the 5 bit block number is put on the XLA bus address lines 15 through 19. If during the system memory access a parity error occurs, a parity error bit is set and a Z-80A NMI is generated. The NMI should sample the parity bit by reading the PIA and then clear the parity error bit. Table 5-19 defines the Z-8riJ memory addressing.
Table 5-19 Z-81 Meaory Addressing 1 MEMORY TYPE 1 Z-80 ADDRESS 1 1 1-----------------1------------------1------------------------1 1 EPROM 1 riJriJH to IFFFH 1 (8K) 1 1 STATIC RAM 1 2riJriJriJ to 27FFH 1{2K) 1 1 SYSTEM MEMORY 1 8riJriJriJ to FFFFH 1 (32 blocks) 1 1 1 1 1 5-26