TABLE OF CONrEftS PAGE SUBJECT 5-25 Z-80A I/O CONTROLLER 5-25 Functional Description 5-26 Z-80A I/O Processor Memory 5-27 80186/Z-80A Comrnunnications 5-28 Host/Controller Communication 5-28 Controller Initialization 5-29 Channel Initialization 5-29 Channel Transmit Operation 5-29 Channel TTY Receive Operation 5-29 Channel Ring Buffered Receive Operation 5-30 Modem Status Operation 5-30 REGISTER DEFINITIONS 5-30 Initialization Register 5-31 Control Registers 5-32 Communication Channel Registers 5-36 HARD DISK CONTROLLER HARDWARE OVERVIEW 5-36 INTRODUCTION 5-36 FUNCTIONAL DESCRIPTION 5-36 Disk Drive Description 5-36 Head Selection 5-39 Formatting Guidelines 6-1 6.
FIRMWARE IN'rERFACB 6-1 INTRODUCTION 6-1 SYSTEM MONITOR 6-3 Monitor Location 6-4 Debugger Program 6-5 Entering the Debugger Program 6-5 Executing a Debugger Command (An example) 6-12 486 Monitor's System Call Interface 6-18 Power-up Test 6-19 Power-up Test Error Reporting Scheme 6-19 Power-up Test Descriptions A-I APPENDIX A. 486 CPU JUMPlCR:mG SPECIFICATIONS B-1 APPENDIX B.
PORT CONNECTIONS ILLUS'l'RATIONS 1-2 Figure 1-1 Altos Model 486 Computer System 3-2 Figure 3-1 Bus Architecture 4-2 Figure 4-1 System Block Diagram 5-2 Figure 5-1 CPU Board Block Diagram 5-8 Figure 5-2 Master/Slave PIC Configuration 5-9 Figure 5-3 Interrupt Request 5-37 Figure 5-4 Hard Disk Controller Board Circuitry 5-40 Figure 5-5 Sector Format A-I Figure A-I CPU Jumper Locations B-5 Figure B-1 Hard Disk Drive