1-3. IC3,4 HM5264165FTT (64Mbit SDRAM (4Mword x16bit)) Wave RAM for Voice LSI The clock changes by the value of sampling frequency. 44.1kHz: 33.869MHz (= fsx768) 48kHz : 36.864MHz (= fsx768) 96kHz : 36.864MHz (= fsx384) If there is no DIMM, SDRAM is placed in zero address. If there is DIMM(s), SDRAM is placed in last address. 1-4. IC5,6 HY57V281620AT-P (128Mbit SDRAM (8Mword x16bit)) CPU work RAM This clock is set to half of CPU core clock by software. (“88.45MHz” When CPU clock is 176.9MHz.) 1-5.
IC7 MBM29DL322TE90TN (32Mbit Flash ROM (2M word x16bits)) CPU Boot ROM (If ROM-card is inserted in J7, system boot up from ROM card.) SERVICE MANUAL 21 Signal name Dir Explanation TxD C _ in CD digital recognition. Low=connected.(MPC only) SCLK C _ in BM1. Machine recognition. Low=Z4/8. High=MPC. SFRM C _ in BM0. Connected GND now. for future. LDD[7:0] out LCD controller display data. L BIAS _ out LCD ac bias drive. L PCLK _ out LCD pixel clock. L LCLK _ out LCD line clock. L FCLK _ out LCD frame clock. TXTAL in Not used.(Clock for CPU’s real-time clock) ROM SEL _ in ROM bus width select. Low=16bits. SMROM EN _ in SMROM enable. Low= disable.
/PIOR,/PIOW out PCMCIA I/o read/write for ROM Emulator /IOIS16 in PCMCIA 16-bit I/O data transfers for ROM Emulator TCK BYP _ TESTCLK in Test pin GP10,/PCE1 /PWAIT BATT FAULT _ VDD FAULT _ out # Not used though this is connected # VDD - Positive supply for the core. +1.75V VDDX - Positive supply for the pins. +3.3V VSS - Ground supply. VSSX - Ground supply for the I/O pins.