User Manual of EM730 Series Inverter 80 122: wiring detection signal 123: brake reset terminal F02.15 Positive/negati ve logic 1 of digital input terminal D7 D6 D5 D4 D3 D2 D1 D0 00000 〇 0x020F * * * X5 X4 X3 X2 X1 0: positive logic, valid in the closed state/invalid in the open state 1: negative logic, invalid in the closed state/valid in the open state F02.16 Positive/negati ve logic 2 of digital input terminal D7 D6 D5 D4 D3 D2 D1 D0 00 〇 0x0210 * * * * * * AI2 AI1 0: positive logic, valid in the closed state/invalid in the open state 1: negative logic, invalid in the closed state/valid in the open state F02.17 Filtering times of digital input terminal 0~100, 0: no filtering; n:
sampling every n ms 2 〇 0x0211 F02.18 X1 valid delay time 0.000~30.000 s 0.000 ● 0x0212 F02.19 X1 invalid delay time 0.000~30.000 s 0.000 ● 0x0213 F02.20 X2 valid delay time 0.000~30.000 s 0.000 ● 0x0214 F02.21 X2 invalid delay time 0.000~30.000 s 0.000 ● 0x0215 F02.22 X3 valid delay time 0.000~30.000 s 0.000 ● 0x0216 F02.23 X3 invalid delay time 0.000~30.000 s 0.000 ● 0x0217 F02.24 X4 valid delay time 0.000~30.000 s 0.000 ● 0x0218 F02.25 X4 invalid delay time 0.000~30.000 s 0.000 ● 0x0219 F02.26 Minimum input pulse 0.00 to maximum input pulse frequency F02.28 kHz 0.00 ● 0x021A