If no error is detected in the static test, a dynamic test using the actual interrupt capability will be tested in the Internal CPU's Interrupt Test. 12) Internal CPU's Timer Test - Two data patterns (Number 0000 and Number ffff) are used in a static test to write and read to all three internal l86's timer registers. These two patterns will detect any possible short-circuits with ground and +5 Volt. If no error is detected in the static test, a dynamic test will be conducted. In the dynamic test, all three timers are first programmed with a maximum count of 256. Then, all three timers are started and stopped in a very short time.
At this point all three count registers are checked to see if they have ever been incremented. If so, the CPU's timers are working. NOTE The timer's interrupt capablity is tested in the next test. 13) Internal CPU's Interrupt Test - This test verifies the interrupt capability of the CPU-80l86. First, all CPU interrupt vectors are set to an error code, except timer 0's interrupt. Next, the CPU's interrupt controller and timer 0's interrupt service routine are both programmed for timer 0's interrupt. Then timer.0 is started and the program enters a wait loop.
If timer 0 interrupts and the correct service routine is entered, this test is passed, otherwise, if the wait loop is exhausted or there is no response from the service routine, an error is reported. 14) Internal CPU's DMA Test - This test verifies the DMA capability of the CPU-80l86. Since there are as many as 108 possible combinations of the CPU's DMA transfer modes, only six general tests are performed in this test. They are as follow:
1) Word transfer with both source and destination pointers incremented.* 2) Byte transfer with both source and destination pointers incremented.* 3) Word transfer with both source and destination pointers remaining the same.* *Refer also to DMA source and destination register offsets in Chapter 5. 6-22