FLOPPY DISK DRIVE The floppy disk circuitry is controlled through the 765 chip and interrupts the microprocessor via the 8255 parallel interface port. Control and read/write signals to and from the disk drive are handled through connector J7 on the CPU. The PLL (Phase Lock Loop) aids the 765 in recovering MFM (Modified Frequency Modulation) data. WORKNET WorkNet enables the 486 to be connected to a network of other Altos computers using synchronous data link control (SDLC). WorkNet conforms to an RS422 electrical standard. To implement WorkNet, the 486 systems dedicates one of its two DMA channels for this function. A circuit then generates 800 KHz for the network baud rate.
Z-80A I/O PROCESSOR PROM that is local to the Z-80A. It also uses a small amount of static RAM for temporary storage and buffering. The I/O processor communicates with the central processor via system memory locations and interrupts. It supports five RS232 The Z-80A I/O processor runs a control program that resides in a channels. The Z-80A 64K of memory space is divided into two halves. The upper 32K is mapped into the system memory and the lower 32K is mapped into the local PROM and static RAM. The Z-80A can access the full 512 Kbytes of memory but must do so in blocks of 32 Kbytes each. BARD DISI COJrmOLLER BOARD The other major subsystem of the 486 is the Hard Disk Controller unit.
The main component on the board is the WD10l0 Winchester chip. The WD10l0 Winchester drive controller chip controls the Hard Disk Drive. Read/write instructions from the micro- processor enter the Hard Disk Controller board through the J10 connector. The command is then sent to the WD10l0 Controller which controls and monitors a 512 byte buffer used to hold read or write data. One hard disk sector 512 bytes of information. Data is transferred to and from the 20 Mbyte disk drive. 4-4