Data transfers may be either source or destination synchronized, that is, either the source of the data or the destination of the data may request the data transfer. In addition, DMA transfers may be unsynchronized, that is, transfers take place continually until the correct number of transfers has occurred. To perform a DMA channel transfer, the channel program provides information that describes the operation by loading values into channel registers. DMA cycles can run in either Supervisor or User state and must be permitted to run without triggering access protection mechanism.
Table 5-1 Chip Select Register Offset 1 ADDRESS (HEX) 1 DESCRIPTION 1 1-------------------1--------------------1 1 A0H 1 UPPER MEM CS 1 1 A2H 1 LOWER MEM CS 1 1 A4H 1 PACS REGISTER 1 1 A6H 1 MID RANGE MEM CS 1 1 A8H 1 MPCS REGISTER 1 1 1 1 Table 5-2 DMA Register Offsets ADDRESS (HEX) DESCRIPTION 1 CHANNEL 1 1 1 1 CH 0 1 1 CH 0 1 1 CH 0 1 1 CH 0 1 1 CH 0 1 1 CH 0 1 1 CH 1 1 1 CH 1 1 1 CH 1 1 1 CH 1 1 1 CH 1 1 1 CH 1 1 _________________ ---------------------------1 1 ---------------------------1----------------1 FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFD0H FFD2H FFD4H FFD6H FFD8H FFDAH SOURCE POINTER SOURCE POINTER DESTINATION POINTER DESTINATION POINTER TRANSFER COUNT CONTROL WORD SOURCE POINTER SOURCE POINTER DESTINATION POINTER DESTINATION POINTER TRANSFER COUNT CONTROL WORD 5-5