Table 5-13 PIA Port Address Offsets ADDRESS (HEX) I FUNCTION -----------------------_._----------------------- 2D0 I PORT A READ OR WRITE 2D2 I PORT B READ OR WRITE 2D4 I PORT C READ OR WRITE 2D6 I CONTROL/BIT SET REGISTER Three basic modes of operation may be selected under program control mode 0--basic I/O; mode l--strobed I/O; mode 2-- bidirectional bus. Port C, under modes 1 and 2 operation, provide control (handshaking) signals for asynchronous operation. Modes 1 and 2 are also supported by interrupt I/O capability. FLOPPY DISK CONTROLLER OPERATION The Floppy Disk Controller (FDC) is an LSI chip, the uPD765, which contains the circuitry for interfacing a processor to the disk drive.
In this application, it supports a single double- sided, double-density (MFM) 5-1/4 inch drive. The FDC has a buil t-in data separator. The FDC shares one of the two DMA channels with the Hard Disk Controller board. Thus the processor need only load the command into the FDC, after which the data transfer occurs under control of the FDC and the 80186. The FDC is capable of multisector transfers. Fifteen commands can be executed by the FDC, including the basic read, write, scan, format, seek, recalibrate, sense status, and their variations. Details of each command are found in the manufacturer's data handbook.
Two internal registers in the FDC may be accessed by_ the 80186 a status register and a data register See Table 5-14 and 5-15. The 8-bit status register may be read at any time. The data register actually consists of a stack of 8-bit registers, only one of which can be latched to the bus at one time. Programming The track stepping rate, head load time, and head unload time, are not programmable in this application but are hardwired into the controller circuitry. 5-24